CD74HC221M96 Electronic IC Chips CMOS Logic Dual Monostable Multivibrator

CD54HC221, CD74HC221, CD74HCT221

High-Speed CMOS Logic Dual Monostable Multivibrator with Reset

Features

• Overriding RESET Terminates Output Pulse

• Triggering from the Leading or Trailing Edge

• Q and Q Buffered Outputs

• Separate Resets

• Wide Range of Output-Pulse Widths

• Schmitt Trigger on B Inputs

• Fanout (Over Temperature Range)

  - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

  - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55℃ to 125℃

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL Logic ICs

• HC Types

  - 2V to 6V Operation

  - High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V

• HCT Types

  - 4.5V to 5.5V Operation

  - Direct LSTTL Input Logic Compatibility, V_IL= 0.8V (Max), V_IH = 2V (Min)

  - CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH

Pinout

Description

The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (R_X) and an external capacitor (C_X) control the timing and the accuracy for the circuit. Adjustment of R_X and C_X provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse.

Once triggered, the outputs are independent of further trigger inputs on A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing Edge triggering (A) and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low.

The minimum value of external resistance, R_X, is typically 500Ω. The minimum value of external capacitance, C_X, is 0pF. The calculation for the pulse width is tW = 0.7 R_XC_X at V_CC = 4.5V.

Absolute Maximum Ratings

DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I_IK

  For V_I < -0.5V or V_I > V_CC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I_OK

  For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I_O

  For -0.5V < V_O < V_CC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I_O

  For V_O > -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC V_CC or Ground Current, I_CC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Logic Diagram

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