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Output Frequency: | 1450 MHz To 1750 MHz | Volitage: | 3.0V To 3.6V |
---|---|---|---|
Current: | ±100 A | Temperature: | –40°C To +85°C |
Mode: | Integrated Synthesizer And VCO | Function: | Control |
Highlight: | electronics ic chip,integrated circuit ic |
ADF4360-4BCPZ new / original IC Chip Integrated Synthesizer and VCO
FEATURES
Output frequency range: 1450 MHz to 1750 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17, 32/33
Programmable output power level 3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
GENERAL DESCRIPTION
The ADF4360-4 is a fully integrated integer-N synthesizer and voltage-controlled oscillator (VCO). The ADF4360-4 is designed for a center frequency of 1600 MHz. In addition, a divide-by-2 option is available, whereby the user gets an RF output of between 725 MHz and 875 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Table 3.
Parameter | Rating |
AVDD to GND1 AVDD to DVDD VVCO to GND VVCO to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND Operating Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance (Paddle Soldered) (Paddle Not Soldered) Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) |
−0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V
150°C
50°C/W 88°C/W 215°C 220°C |
TRANSISTOR COUNT
12543 (CMOS) and 700 (Bipolar)
CIRCUIT DESCRIPTION REFERENCE INPUT SECTION
The reference input stage is shown in Figure 10. SW1 and SW2 are normally closed switches. SW3 is normally open.When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down
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