Anterwell Technology Ltd.
Large Original stock of IC Electronics Components, Transistors, Diodes etc.
High Quality, Reasonable Price, Fast Delivery.
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I/O Read: | Prefetching Never Allowed | Configuration Read: | Prefetching Never Allowed |
---|---|---|---|
Memory Read: | Downstream: Prefetching Used If Address Is Prefetchable Space | Memory Read Line: | Prefetching Always Used |
Memory Read Multiple: | Prefetching Always Used | ||
Highlight: | digital integrated circuits,linear integrated circuits |
Product Description
The PI7C8152A and PI7C8152B (PI7C8152x) are Pericom Semiconductorís PCI-to-PCI Bridge that are designed to be fully compliant with the 32-bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C8152B supports both synchronous and asynchronous bus transactions between devices on the Primary Bus and the Secondary Buses operating up to 66MHz. The PI7C8152A supports synchronous transactions only. In synchronous mode, both buses must operate at the same frequency. The Primary and Secondary Bus can also operate in concurrent mode, resulting in added increase in system performance.
Product Features
• 32-bit Primary and Secondary Ports run up to 66MHz
• Compliant with the PCI Local Bus Specification, Revision 2.2
• Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1.
− All I/O and memory commands
− Type 1 to Type 0 configuration conversion
− Type 1 to Type 1 configuration forwarding
− Type 1 configuration write to special cycle conversion
• Compliant with the Advanced Configuration Power Interface (ACPI) Specification
• Compliant with the PCI Power Management Specification, Revision 1.1.
• Synchronous and Asynchronous operation support
Signal Types
Signal Type | Description |
I | Input Only |
O | Output Only |
P | Power |
TS | Tri-State bi-directional |
STS | Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when deasserting. |
OD | Open Drain |
FAST BACK-TO-BACK WRITE TRANSACTIONS
PI7C8152x is capable of decoding and forwarding fast back-to-back write transactions. When PI7C8152x cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit must be set in the command register for upstream write transactions, and in the bridge control register for downstream write transactions.
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