LF357N Integrated Circuit Electronics Components amplifier ic chip in electronics

LF357N Integrated Circuit Electronics Components amplifier ic chip in electronics

LF155/LF156/LF256/LF257/LF355/LF356/LF357

JFET Input Operational Amplifiers

General Description

These are the first monolithic JFET input operational amplifiers to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FET™ Technology). These amplifiers feature low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection.

The devices are also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner.

Features

Advantages

• Replace expensive hybrid and module FET op amps
• Rugged JFETs allow blow-out free handling compared with MOSFET input devices
• Excellent for low noise applications using either high or low source impedance — very low 1/f corner
• Offset adjust does not degrade drift or common-mode rejection as in most monolithic amplifiers
• New output stage allows use of large capacitive loads (5,000 pF) without stability problems
• Internal compensation and large differential input voltage capability

Applications

• Precision high speed integrators
• Fast D/A and A/D converters
• High impedance buffers
• Wideband, low noise, low drift amplifiers
• Logarithmic amplifiers
• Photocell amplifiers
• Sample and Hold circuits

Common Features

• Low input bias current: 30pA
• Low Input Offset Current: 3pA
• High input impedance: 1012Ω
• Low input noise current: 0.01pA/√Hz
• High common-mode rejection ratio: 100 dB
• Large dc voltage gain: 106 dB

Uncommon Features

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Note 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum available power dissipation at any temperature is PD=(TJMAX−TA)/θJA or the 25˚C PdMAX, whichever is less.

Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

Simplified Schematic