LPC1769FBD100 LPC17xx User manual microchips and integrated circuits linear digital integrated circuits

LPC1769FBD100 LPC17xx User manual microchips and integrated circuits linear digital integrated circuits

. Introduction

                        The system control block includes several system features and control registers for a                                  number of functions that are not related to specific peripheral devices. These include:

                              • Reset                                                                                                                                                           • Brown-Out Detection                                                                                                                                   • External Interrupt Inputs                                                                                                                               • Miscellaneous System Controls and Status                                                                                                 • Code Security vs. Debugging 

                            Each type of function has its own register(s) if any are required and unneeded bits are                               as reserved in order to allow future expansion. Unrelated functions never e                                                 ddresses

On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset, External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time (maximum of 60 μs on power-up) and after the IRC provides a stable clock output, the reset signal is latched and synchronized on the IRC clock. Then the following two sequences start simultaneously:

1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times out. The boot code performs the boot tasks and may jump to the flash. If the flash is not ready to access, the Flash Accelerator will insert wait cycles until the flash is ready.

2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is de-asserted. The flash wakeup-timer generates the 100 μs flash start-up time. Once it times out, the flash initialization sequence is started, which takes about 250 cycles. When it’s done, the Flash Accelerator will be granted access to the flash.

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