Sn74ls90n Decade , Divide-By-Twelve And Binary Counters Crt Tv Components

SN74LS90N DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS crt tv components

    The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).

• Low Power Consumption ...Typically 45 mW

• High Count Rates ...Typically 42 MHz

• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, Binary

• Input Clamp Diodes Limit High Speed Termination Effects

FUNCTIONAL DESCRIPTION

The LS90, LS92, and LS93 are 4-bit ripple type Decade, Divide-By-Twelve, and Binary Counters respectively. Each device consists of four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight (LS93) section. Each section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The Q0 output of each device is designed and specified to drive the rated fan-out plus the CP1 input of the device.

A gated AND asynchronous Master Reset (MR1 • MR2) is provided on all counters which overrides and clocks and resets (clears) all the flip-flops. A gated AND asynchronous Master Set (MS1 • MS2) is provided on the LS90 which overrides the clocks and the MR inputs and sets the outputs to nine (HLLH).

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